As a method for testing a semiconductor integrated circuit, scan test is known. The scan test is performed by having a scan test circuit (also simply known as “scan circuit”) constituted by a shift register take in test data in parallel (sample mode operation and scan capture operation), serially shift the test data taken in, and output the result (shift mode operation and scan shift operation).
In recent years, the test time required to perform a scan test has increased due to an increase in the circuit scale of semiconductor integrated circuits. As a result, the reduction of the test time is demanded to reduce costs. In order to shorten the test time required to perform a scan test, it is preferable that the frequency of a clock signal that drives the shift register during the shift mode operation be raised. However, if one continues to raise the frequency of the clock signal, the current consumption will increase and the possibility that the operation will be gradually destabilized will increase since a high-frequency clock signal will be supplied.
In order to solve the problem above, a technology that makes the frequency of the clock signal into half by disposing flip-flops constituting a shift register alternately between a flip-flop operating on the rising edge of the clock signal and a flip-flop operating on the falling edge of the clock signal, and having them shift-operate is known (refer to Patent Documents 1 to 3). According to such a technology, the current consumption can be reduced and the operational stability increases since adjacent flip-flops operate on clock edges different from each other.    [Patent Document 1] Japanese Patent Kokai Publication No. JP-P2005-69931A    [Patent Document 2] Japanese Patent Kokai Publication No. JP-A-9-320290    [Patent Document 3] Japanese Patent No. JP2576657B